EDN

Aldec granted new patent on automatic ASIC prototyping

Aldec, Inc., which specializes in in mixed-language simulation, hardware accelerators, and prototyping tools has been awarded a new US Patent for the automatic conversion of ASIC designs into FPGA ...
New Electronics

Aldec releases latest version of the Riviera-PRO

Aldec has said that it is now supplying the most comprehensive implementation of VHDL 2019 for both Windows and Linux platforms with the latest release of Riviera-PRO (release version 2021.04).
Business Wire

Aldec Sets a New Paradigm with a Single Platform for Design Rule Checking and Clock Domain Crossing Verification for FPGA and ASIC Designs

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc. announced today the latest release of its mixed-language Design Rule Checking (DRC) and Clock Domain Crossing (CDC) verification platform, ALINT-PRO™ 2017 ...
Design-Reuse

Aldec, Cadence, Proximus Utilize OVP Fast Processor Models in System Design Solutions

OXFORD, United Kingdom, June 3, 2011 – Imperas™ today announced that its Open Virtual Platforms™ (OVP™) OVPsim simulator and OVP Fast Processor Models™ have been integrated with Aldec’s Hardware ...
Business Wire

Aldec Adds VHDL Standard 1076-2018 Extensions and Automatic Coverage Model Generation to Riviera-PRO™

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., an industry leader in electronic design verification, has added VHDL-2018 interfaces and automatic coverage model generation to its Riviera-PRO™ advanced ...
Yahoo Finance

SmartDV, Aldec Partner to Link SmartDV’s Verification IP with Aldec’s Riviera-PRO Simulator

SAN JOSE, Calif. and HENDERSON, Nev., July 20, 2020 (GLOBE NEWSWIRE) -- SmartDV™ Technologies, the Proven and Trusted choice for Design and Verification Intellectual Property (IP), and Aldec today ...
New Electronics

Aldec adds UVM Generator to Riviera-PRO

Aldec, a specialist in mixed HDL language simulation and hardware-assisted verification for FPGA, ASIC and SoC designs, has added an automatic UVM Generator function to Riviera-PRO. The addition is ...
EDN

Aldec sues Xilinx over expired agreement

SAN MATEO, Calif.—EDA tool vendor Aldec Inc. is seeking a preliminary injunction in San Francisco's Federal Court to stop Xilinx Inc. from distributing Aldec's ActiveParts tools as part of Xilinx's ...
Design-Reuse

Aldec's HES UltraScale+ Reconfigurable Accelerator and Northwest Logic's PCI Express Cores Provide Proven PCI Express Solution

Henderson, NV. – April 11th, 2018 – Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has used Aldec’s HES-XCVU9P-QDR UltraScale+ ...
Semiconductor Engineering

Virtual Modeling With Aldec And Imperas

How to simulate and debug virtual models of processors, memories and peripherals without slowing down the rest of the emulation process. Virtual platforms play a significant role in system level ...
SiliconIndia

Aldec unveils RTL simulator with enhanced assertions

San Francisco: EDA vendor Aldec Corporation has unveiled its new Register Transfer Level (RTL) and gate level simulator for FPGA design and verification engineers. The company says that the Active-HDL ...