The testing and verification of semiconductor chips was a prominent topic at this year’s European Test Systems (ETS) conference, especially in the area of Design-for-Test (DFT) tools and techniques.

Design-for-test, or DFT, should facilitate high-quality test, not change the design. Test techniques and strategies need to supply a high-quality test that screens out defective devices, avoiding ...

Historically, testability is an afterthought in the design process. But heightening complexity of chip designs, and especially SoCs, forces testability (and manufacturability) to take a more central ...

New manufacturing test challenges are raised with SoC technology advances where both test quality and test costs are affected with a direct impact on current Design-For-Test (DFT) methodologies and ...

Until very recently, semiconductor design, verification, and test were separate domains. Those domains have since begun to merge, driven by rising demand for reliability, shorter market windows, and ...

ALLENTOWN, PA—Developing an effective design and test strategy for an IC can be a daunting task. At Agere Systems, the difficulties are magnified because the company produces hundreds of distinct ...

In today’s highly competitive semiconductor industry, chip-design companies strive for competitive advantages by optimizing designs for PPA (Power, Performance, Area). Along with the functional logic, ...

Join us on Wednesday, December 15 at noon Pacific for the Design for Test Hack Chat with Duncan Lowder! If your project is at the breadboard phase, or even if you’ve moved to a PCB prototype, it’s ...

By following optimum practices in material characterization, specimen preparation, alignment, measurement techniques, and ...