EDN

Microsemi’s Libero SoC v11.7 Software Increases Security, Usability and Efficiency for FPGA Designs, Enabling Faster Time-to-Market

“The release of our Libero SoC v11.7 software offers a significantly improved user experience due to a new and enhanced constraints flow with a new constraints management view, a fully redesigned ...
Design-Reuse

Actel Enhances Libero Integrated Design Environment for its Successful ProASICPLUS FPGAs

Version 5.0 Offers More Than 60 Percent Performance Improvement; Adds New Ease-of-Use Features; and Extends Interfaces to Industry-Leading Tools SUNNYVALE, Calif., August 4, 2003 - Actel Corporation ...
New Electronics

First integrated FPGA-in-the-loop workflow for PolarFire and SmartFusion2 FPGA development boards

Microsemi has announced a collaboration with MathWorks to launch hardware support for field programmable gate array (FPGA)-in-the-loop (FIL) verification workflow with Microsemi FPGA development ...
Design-Reuse

Actel Delivers Secure, Comprehensive Design Flow for Complex FPGA Development Using ARM7 Family Processor

Company's Libero IDE Also Bolsters Industry-Leading Static Timing Analysis and I/O Capabilities MOUNTAIN VIEW, Calif., Nov 02, 2005-- Actel Corporation (Nasdaq: ACTL) today unveiled significant new ...
New Electronics

Libero SoC v11.8 software provides debugging capabilities

The latest version of Microsemi’s Libero SoC software – version 11.8, a comprehensive suite of FPGA design tools – has been released. In addition to the software release, which includes enhancements ...
Yahoo Finance

Microchip Further Protects FPGA-based Designs with First Tool that Combats Major Industry Threat to System Security in the Field

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Embedded

FPGA tool upgrade slashes runtime

Microsemi’s Libero SoC design suite V12.0 reduces design flow runtimes, while providing a unified platform for multiple FPGA families, including the latest PolarFire production releases. Improving ...